When designing electronic circuits manufactured in submicrometric CMOS technologies and integrated on a semiconductor substrate, the insertion of electrically non-active service structures is becoming more necessary. These structures are commonly defined as dummy structures. Dummy structures provide an improved definition during the manufacturing process of the electrically active components of an integrated circuit.
Dummy structures, provided in the manufacturing steps of integrated circuits, is considered critical for a predetermined technology, in that they allow the local density of the electrically active structures to be increased. The active structures are to be integrated on a same semiconductor substrate. In fact, these dummy structures, manufactured with semiconductor elements projecting from the semiconductor substrate, having for example a polygonal section, considerably reduce size and shape differences between electrically active structures located at the edges of very structure-dense circuit areas and those located inside the areas.
Moreover, the use of layer removal techniques by circuit-structure-morphology-sensitive tools, such as chemical mechanical polishing (CMP), further makes the insertion of dummy structures necessary since their presence also helps to reduce as much as possible any height differences between the dense areas of electrically active components.
To define a plurality of circuit structures on a semiconductor substrate, a photo-resist material mask is formed on the semiconductor substrate. The geometry of the circuit structures to be manufactured, generally defined as a layout, is etched.
A circuit layout, which does not provide the use of dummy structures at the active area level is shown in FIG. 1 as a non-limiting example. In particular, FIG. 1 shows a photo-resist material mask 1 corresponding to the geometries of the active areas of an electronic circuit to be manufactured on a semiconductor substrate. In particular, the electronic circuit comprises a first portion 3 integrating a FLASH memory matrix, and a second portion 2 integrating the corresponding circuitry.
A FLASH memory matrix comprises a plurality of electrically active structures, for example floating gate MOS transistors, while the circuitry comprises conventional MOS transistors for example. To make uniform the structures provided on the semiconductor substrate, a plurality of active areas is also provided in the layout, i.e., substrate portions delimited by a field oxide, to manufacture a plurality of dummy structures 4, as shown in FIG. 2.
The layout of these dummy structures 4 almost always occurs automatically based upon technology exploiting software tools commonly used by those skilled in the art. Although advantageous under several aspects, this approach has several drawbacks.
In fact, an excessive integration of electronic components on a same semiconductor substrate 1 requires a dedicated optimization of some process steps that are necessary to manufacture the electrically active structures forming the electronic components. Sometimes this requires the definition or “split” of a predetermined manufacture level of these structures. This implies that different photolithographic masks are used to define different circuit portions to be manufactured on a same semiconductor substrate.
For example, in the case of the circuit layout shown in FIG. 2, when the sizes of electrically active cells are reduced, the definition of the active areas of these structures of the Flash cell matrix and of the circuitry requires the use of two different photolithographic masks. This is necessary to form insulation layers having a different thickness.
Since Flash memory cell matrixes are formed by dense structures, i.e., particularly close to each other, and they are generally already drawn with dummy structures, particularly dummy cells, to take into consideration some photolithographic definition edge effects, the active areas of dummy structures 4 are provided on the semiconductor substrate 1, and when generating masks, they are associated to the electrically active structures.
Thus, when the size of electrically active structures is reduced, the need to optimize the definition of the active areas of very dense electrically active structures with respect to less dense ones is increasingly felt.
Nevertheless, when the memory matrix area portion is proportionally a negligible fraction with respect to the sizes of the whole electronic circuit, some process problems can occur with the presently available tools and equipment making it difficult to define correctly the active matrix area.